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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM72BF32/D
256KB and 512KB BurstRAMTM Secondary Cache Module for PentiumTM
The MCM72BF32SG and MCM72BF64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 160 pin card edge memory module. Each module uses four of Motorola's MCM67B518 or MCM67B618 BiCMOS BurstRAMs. All 72 I/Os are series terminated for added noise immunity. Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with popular Pentium cache controllers with on board tag. PD0 - PD2 are reserved for density identification. * Pentium-style Burst Counter on Chip * Flow-Through Data * 160 Pin Card Edge Module * Single 5 V 5% Power Supply * All Inputs and Outputs are TTL Compatible * Three State Outputs * Byte Parity, Byte Write Enables * Fast Module Clock Rates: 66 MHz, 60 MHz * Decoupling Capacitors for each Fast Static RAM * High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes * I/Os are 3.3 V Compatible * Burndy Connector, Part Number: CELP2X80SC3Z48 * Series 20 Resistors for Noise Immunity
MCM72BF32 MCM72BF64
160-LEAD CARD EDGE CASE 1113A-01 TOP VIEW
1
42 43
80
BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp.
5/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM72BF32*MCM72BF64 1
PIN ASSIGNMENT 160-LEAD CARD EDGE MODULE TOP VIEW
PD2 VSS VSS
PD1 VSS VSS
PD0 NC VSS
Cache Size 256KB 512KB
Module 72BF32SG 72BF64SG
VSS DQ63 VCC5 DQ61 VCC5 DQ59 DQ57 VSS DQP7 DQ55 DQ53 DQ51 VSS DQ49 DQ47 DQ45 DQ43 VSS DQ41 DQP5 DQ39 DQ37 DQ35 VSS DQ33 DQ31 DQ29 DQ27 DQ25 VSS DQP3 DQ23 DQ21 VCC5 DQ19 VSS DQ17 VCC5 DQ15 DQ13 VSS DQ11 VCC5 DQ9 DQP1 VCC5 DQ7 DQ5 DQ3 DQ1 VSS A3B A4B A5B A6B A7 VSS A9 A11 A13 A15 A17 VSS *A19 PD1 K0 *K2 VSS W7 W5 W3 W1 VSS ADSC1 E1 ADV1 G1 VCC5 ADSP1 VSS
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VSS DQ62 VCC3* DQ60 VCC3* DQ58 DQ56 VSS DQP6 DQ54 DQ52 DQ50 VSS DQ48 DQ46 DQ44 DQ42 VSS DQ40 DQP4 DQ38 DQ36 DQ34 VSS DQ32 DQ30 DQ28 DQ26 DQ24 VSS DQP2 DQ22 DQ20 VCC3* DQ18 VSS DQ16 VCC3* DQ14 DQ12 VSS DQ10 VCC3* DQ8 DQP0 VCC3* DQ6 DQ4 DQ2 DQ0 VSS A3A A4A A5A A6A A8 VSS A10 A12 A14 A16 A18** VSS PD0 PD2 K1 K3* VSS W6 W4 W2 W0 VSS ADSC0 E0 ADV0 G0 VCC3* ADSP0 VSS
PIN NAMES
A3 - A18 . . . . . . . . . . . . . . . . . . . . . . Address Inputs K0, K1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock W0 - W7 . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Write E0, E1 . . . . . . . . . . . . . . . . . . . . . . . . Module Enable G0, G1 . . . . . . . . . . . . . . . . . Module Output Enable DQ0 - DQ63 . . . . . . . . . . Cache Data Input/Output DQP0 - DQP7 . . . . . . . . . Data Parity Input/Output ADSC0, ADSC1 . . . . . . Controller Address Status ADSP0, ADSP1 . . . . . . Processor Address Status ADV0, ADV1 . . . . . . . . . . . . . . . . . . . Burst Advance PD0 - PD2 . . . . . . . . . . . . . . . . . . Presence Detect VCC5 . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VCC3 . . . . . . . . . . . . . . . . . . . + 3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
* No Connect for MCM72BF32/MCM72BF64 ** No Connect for MCM72BF32
MCM72BF32*MCM72BF64 2
MOTOROLA FAST SRAM
64K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
MCM67B618 A7 - A18 A3A - A6A ADSP0 ADSC0 ADV0 K0 G0 E0 12 4 A4 - A15 A0 - A3 ADSP ADSC ADV K G E DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 LW 8 DQ0 - DQ7 DQP0 W1 DQ8 - DQ15 DQP1 W0
MCM67B618 LW A4 - A15 A0 - A3 ADSP ADSC ADV K G E DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 8
W2
DQ16 - DQ23 DQP2 W3 DQ24 - DQ31 DQP3
MCM67B618 A4 - A15 A3B - A6B ADSP1 ADSC1 ADV1 K1 G1 E1 4 A0 - A3 ADSP ADSC ADV K G E DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 LW 8 DQ32 - DQ39 DQP4 W5 DQ40 - DQ47 DQP5 W4
MCM67B618 LW A4 - A15 A0 - A3 ADSP ADSC ADV K G E DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 8
W6
DQ48 - DQ55 DQP6 W7 DQ56 - DQ63 DQP7
DQ0 - DQ63 and DQP0 - DQP7 have 20 series termination resistors.
MOTOROLA FAST SRAM
MCM72BF32*MCM72BF64 3
32K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
A18 A7 - A17 A3A - A6A ADSP0 ADSC0 ADV0 K0 G0 E0 11 4
NC
MCM67B518 A4 - A14 A0 - A3 ADSP ADSC ADV K G E DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 LW 8 DQ0 - DQ7 DQP0 W1 DQ8 - DQ15 DQP1 W0
MCM67B518 LW A4 - A14 A0 - A3 ADSP ADSC ADV K G E DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 8
W2
DQ16 - DQ23 DQP2 W3 DQ24 - DQ31 DQP3
MCM67B518 A4 - A14 A3B - A6B ADSP1 ADSC1 ADV1 K1 G1 E1 4 A0 - A3 ADSP ADSC ADV K G E DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 LW 8 DQ32 - DQ39 DQP4 W5 DQ40 - DQ47 DQP5 W4
MCM67B518 LW A4 - A14 A0 - A3 ADSP ADSC ADV K G E DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 8
W6
DQ48 - DQ55 DQP6 W7 DQ56 - DQ63 DQP7
DQ0 - DQ63 and DQP0 - DQP7 have 20 series termination resistors.
MCM72BF32*MCM72BF64 4
MOTOROLA FAST SRAM
MCM67B618 BLOCK DIAGRAM (See Note)
ADV BURST LOGIC Q0 BINARY COUNTER K A0 16 Q1 A1 A1 A0 INTERNAL ADDRESS 64K x 18 MEMORY ARRAY
ADSC ADSP
CLR
2 A0 - A15 ADDRESS REGISTER 16 A1 - A0 A2 - A15 18 9 9
UW LW
WRITE REGISTER
DATA-IN REGISTERS
E
ENABLE REGISTER 9 9 9 9
OUTPUT BUFFER
G DQ0 - DQ8 DQ9 - DQ17
NOTE: All registers are positive-edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP-initiated two cycle WRITE can be performed by asserting ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE (See Note)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A15 - A2 A15 - A2 A15 - A2 A15 - A2 A1 A1 A1 A1 A0 A0 A0 A0
NOTE: The burst wraps around to its initial state upon completion.
MOTOROLA FAST SRAM
MCM72BF32*MCM72BF64 5
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E H H L L L X X X X ADSP L X L H H H H H H ADSC X L X L L H H H H ADV X X X X X L L H H UW or LW X X X L H L H L H K L-H L-H L-H L-H L-H L-H L-H L-H L-H Address Used N/A N/A External Address External Address External Address Next Address Next Address Current Address Current Address Operation Deselected Deselected Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means Don't Care. 2. All inputs except G must meet setup and hold times for the low-to-high transition of clock (K). 3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Read Write Deselected G L H X X I/O Status Data Out High-Z High-Z -- Data In High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 6.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MCM72BF32*MCM72BF64 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.75 2.2 - 0.5* Max 5.25 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20.0 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20.0 ns) for I 20.0 mA.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G = VIH) AC Supply Current (G = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) Output Low Voltage (IOL = + 8.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA66 ICCA60 ISB1 VOL Min -- -- -- -- -- Max 1.0 1.0 1100 1060 380 0.4 Unit A A mA mA V
Output High Voltage (IOH = - 4.0 mA) VOH 2.4 3.3 V NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible Pentium bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input Capacitance Input/Output Capacitance (A7 - A18) (A3x - A6x, ADSPx, ADSCx, ADVx, Kx, Gx, Ex, Wx) (DQ0 - DQ63, DQP0 - DQP7) Symbol Cin Cin CI/O Max 20 10 8 Unit pF pF pF
MOTOROLA FAST SRAM
MCM72BF32*MCM72BF64 7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) (Wx refers to any or all byte write enables)
MCM72BF64SG66 Parameter Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Symbol tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH Address tAVKH Address Status tADSVKH tDVKH Data In tWVKH Write Address Advance tADVVKH tEVKH Chip Enable Address tKHAX Address Status tKHADSX tKHDX Data In tKHWX Write Address Advance tKHADVX tKHEX Chip Enable Min 15 -- -- 6 3 0 2 -- 5 5 2.5 Max -- 9 5 -- -- -- 6 6 -- -- -- MCM72BF64SG60 Min 16.7 -- -- 6 3 0 2 -- 5 5 2.5 Max -- 10 5 -- -- -- 6 6 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 6 5 4 Notes
Hold Times:
0.5
--
0.5
--
ns
6
NOTES: 1. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP high for the setup and hold times. 2. All read and write cycle timings are referenced from K or G. 3. G is a don't care when UW or LW is sampled low. 4. Maximum access times are guaranteed for all possible Pentium external bus cycles. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device. 6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is enabled.Chip enable must be valid at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled.
AC TEST LOADS
+5V 480 OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF
Figure 1A
Figure 1B
MCM72BF32*MCM72BF64 8
MOTOROLA FAST SRAM
READ CYCLES
t KHKH
t KHADSX
K t KHKL t KLKH
t ADSVKH
MOTOROLA FAST SRAM
t KHADSX t ADSVKH t KHAX A1 t KHWX t WVKH A2 t KHEX t KHADVX t ADVVKH t KHQV t GLQV (ADV SUSPENDS BURST) t GHQZ Q(A1) t KHQV t KHQX2 Q(A2) Q(A2 + 1) Q(A2 + 2) (BURST WRAPS AROUND TO ITS INITIAL STATE) Q(A2 + 3) Q(A2) Q(A2 + 1) t KHQZ SINGLE READ BURST READ
ADSP
ADSC
t AVKH
ADDRESS
LW, UW
t EVKH
E
ADV
G
t GLQX
DATA OUT
Q(A2 + 2)
MCM72BF32*MCM72BF64 9
NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address.
WRITE CYCLES
t KHKH
K t KHKL t KHADSX t KLKH
t ADSVKH
ADSP t ADSVKH t KHADSX ADSC STARTS NEW BURST
MCM72BF32*MCM72BF64 10
t KHAX A1 W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST A2 A3 t WVKH t KHEX t ADVVKH ADV SUSPENDS BURST t DVKH D(A1) t GHQZ D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) SINGLE WRITE BURST WRITE (WITH A SUSPENDED CYCLE) NEW BURST WRITE
ADSC
t AVKH
ADDRESS
t KHWX
LW, UW
t EVKH
E t KHADVX
ADV
G t KHDX
DATA IN
D(A3 + 2)
DATA OUT
Q(An - 1)
Q(An)
MOTOROLA FAST SRAM
BURST READ
COMBINATION READ/WRITE CYCLE (E low, ADSC high)
tKHKH
K tKHKL tKLKH
tADSVKH ADSP
tKHADSX
tAVKH ADDRESS A1
tKHAX A2 A3
tWVKH LW, UW
tKHWX
tADVVKH ADV
tKHADVX
G tDVKH D(A2) tKHQX1 tGHQZ tGLQX tKHQX2 tKHDX tGLQV
tKHQV DATA IN
DATA OUT
Q(A1)
Q(A3)
Q(A3 + 1)
Q(A3 + 2)
READ
WRITE
BURST READ
MOTOROLA FAST SRAM
MCM72BF32*MCM72BF64 11
APPLICATION EXAMPLE
DATA BUS DATA ADDRESS BUS ADDRESS CLOCK
PentiumTM CLK K
ADDR CACHE CONTROL LOGIC
ADDR DATA K0 K1 ADSC W MCM67B618FN9 G0 G1 ADSP ADV MCM72BF64SG66
ADS CONTROL
512K Byte Burstable, Secondary Cache Using MCM72BF64SG66 with a 66 MHz Pentium Figure 2
ORDERING INFORMATION
(Order by Full Part Number) 72BF32 MCM 72BF64 XX
Motorola Memory Prefix Part Number
XX
Speed (66 = 66 MHz, 60 = 60 MHz) Package (SG = Gold Pad SIMM)
Full Part Numbers -- MCM72BF32SG66 MCM72BF64SG66
MCM72BF32SG60 MCM72BF64SG60
MCM72BF32*MCM72BF64 12
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
160-LEAD CARD EDGE MODULE CASE 1113A-01 A E
COMPONENT AREA
C
NOTE 4
B
-Y- VIEW AA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E
FULL R 80 43 42 1 2X
P
V
NOTE 4
F
AC
-X-
L
M
AB
NOTE 5
J -T- SIDE VIEW
NOTE 6
FRONT VIEW
0.012 (0.3)
M
R
R
W
(N)
EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE
160
EEE E E EEE E E EEE E E EEE E E EEE E E
VIEW AA
123 122
160X
D 0.004 (0.1)
L
TYX
S
160X
H
160X
K
156X
G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND V DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION AB DEFINES OPTIONAL SINGLE-SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. DIM A B C D E F G H J K L M N P R V W AB AC INCHES MIN MAX 4.330 4.350 1.270 1.310 --- 0.454 0.033 0.037 2.265 2.275 0.075 BSC 0.050 BSC --- 0.030 0.055 0.069 0.210 --- 1.955 1.965 2.155 2.165 0.110 REF 0.125 --- 0.285 0.305 0.157 --- 0.040 0.060 --- 0.262 0.072 0.076 MILLIMETERS MIN MAX 109.98 110.49 32.26 33.27 --- 11.53 0.84 0.94 57.53 57.79 1.91 BSC 1.27 BSC --- 0.51 1.40 1.75 5.33 --- 49.66 49.91 54.74 54.99 2.79 REF 3.18 --- 7.24 7.75 3.99 --- 1.02 1.52 --- 6.66 1.83 1.93
81
COMPONENT AREA
BACK VIEW
MCM72BF32*MCM72BF64 13
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM72BF32*MCM72BF64 14
*MCM72BF32/D*
MOTOROLA MCM72BF32/D FAST SRAM

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